Secure-IC provide Chip Security Protection IP Cores: Cryptographic algorithm IP such as AES, DES, 3-DES, ECC, RSA, SM2, SM3, SM4, SHA1, SHA2, SHA3, HMAC, countermeasure IP such as TRNG, CTR-DRBG RNG, Digital Sensor, Active Shield, PUF, Smart Monitor, Scrambled Bus, Memory Ciphering, Cyber CPU, Secure Clock, Secure Book, Secure Monitor, Secure JTAG, etc.
Maximum security-enabling monitoring, Security policy bypass, Digital
Maximum security-enabling monitoring, Security policy bypass, Digital
1. OVERVIEW
The security of a System-on-Chip depends on various tamper protections used to protect the cryptographic keys from different kind of attacks. These keys are usually transmitted as plaintext between heterogonous modules through a SoC interconnect as bus and network-on-chip.
Advance probing techniques consist in approaching probes near an on-chip wire and observe logical values transmitted through it. This technique is applied when the on-chip wire is routed on the top metal layers of the chip.
Another technique, based on the Focused on Beam (FIB) technology, consists of drilling a hole to an on-chip wire routed on bottom metal layers, felling the hole with platinum and creating a pad on surface for easy access.
The probing attacks are expensive but they are more and more used by attackers to retrieve the keys transmitted through the SoC interconnect. Advance probing attacks might use multiple probes and access to full data word carried by the bus. This is why busses should be protected against probing attacks.The typical protection against the probing attacks is shielding using dedicated wires routed above the buses to be protected. The shield protection deteriorates the chip performances in term of area and power consumption when the shield lines cover the whole circuit. To reduce the shield cost, the designer can select only sensitive zones of the chip to be covered with the shield; however, this solution introduces a breach because the buses that transmit sensitive data between the zones covered by the shield remain vulnerable.
Secure-IC Scrambled Bus IP masks all data carried on the bus with random variables generated locally by cryptographic primitives.
Features:
· Cryptographically secure masking
· On-the-fly masking and unmasking, no additional latency
· Transparent for bus masters and slaves, no modifications on the wrappers
· Easy integration
· Adaptable to various protocols
· High frequency (more than 1GHz is reached with 28nm technology)
Secure-IC provide various security IP cores as following list (keep updating).
| AES | Encryption, against Side-Channel Attacks |
| DES / 3-DES | Encryption, against Side-Channel Attacks |
| RSA | Encryption, against Side-Channel Attacks |
| ECC | Encryption, against Side-Channel Attacks |
| HASH (SHA-1/MD-5) | Encryption, against Side-Channel Attacks |
| SM2 | Encryption, against Side-Channel Attacks |
| SM3 | Encryption, against Side-Channel Attacks |
| SM4 | Encryption, against Side-Channel Attacks |
| TRNG | True Random Number Generator，Digital，against Harmonic EM Attacks |
| PUF | Digital, Anti Cloning/Counterfeiting，100% Unique, Random and Steady ID Generation |
| Digital Sensor | Anti Fault Injection Attacks, All-in-one Fault Injection Detector, Entirely Digital |
| Active Shield | Active Protection against Intrusive Attacks on ASIC, Anti Intrusive Hardware Modification. |
| Scrambled BUS | Encrypted Information to Prevent Probing on BUS, Anti Eavesdroping |
| Memory Ciphering | Memory Protection Against Reverse Engineering and Tampering |
| Secure Clock | Anti Synchronization to prevent efficient SCA and FIA |
| Secure JTAG | Authentication System to Secure the debugging channel on chip, Anti JTAG Violation |
| Secure Boot | Maximum security-enabling root-on-trust, Anti Firmware Tampering |
| Secure Monitor | Maximum security-enabling monitoring, Security policy bypass |
| CyberCPU CPU | CPU-agnostic Cyber Attack Sensor |
Current Products:Security IP: Scrambled BUS
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